CoreX3 and EFC master sync confusion

[dwoodlock]

Hello,

I'm workingn on a project with an X3, and an EFC drive communicating between ethercat. I've encountered an issue when the system restarts where the ethercat will not synchronize without intervention.

It ends up that the master goes into PreOp, and the EFC goes to SafeOP.

I was able to work around this by monitoring the ECAT bus, and then changing states. When I see the master go to preOP, I switch it back to initialization, and then from initialization to OP mode. This seems to fix the synchronization issue, but I am just curious if there is a cleaner way of doing this?

Thanks

[CodeWasi · Accepted solution]

The monitoring is useful in any case since the timing e.g. may differ from core and drives. The Ecat status provides an overview to retrigger the OP-switching again (Not all slaves in Masterstate...). The data is available in the Datalayer. PLC provides the data with IL_ECATRead ...