Q1: The EtherCAT communication is a part of the datalayer and integrated in it. How is the cycle time for updating cyclic process data (send and receive)? Is this cylce time configurable?
Q2: When and how is the image of the I/O prcess data stored in the data layer?
Q3: Which additional latencies can the data layer occure?
Q4: Is it possible to create an acylic communication between the Master and Slave? An how can it be done?
Q5: Who is responsible for the start of an acyclic communication? Time scheduling and free slots on data canal?
Q6: Other competitors support an EtherCAT communication with a standard office switch in the topology. If you use an office switch in the ctrlX system, they appears an error "topology mismatch". Why?
... View more